The host will either take any unused processor time from any of the four other VMs or write the other VMs 'data to disc to free up resources. 主机将从任何其他4个VM获取任何未用的处理器时间,或者将其他VM的数据写入磁盘以释放资源。
If your host and guest operating system are targeted to the same processor architecture, then you can speed things up to near native performance using the QEMU accelerator ( KQEMU). 如果主机操作系统和来宾操作系统运行于相同的处理器架构之上,那么您可以使用QEMU加速器(KQEMU)实现近似本地的性能。
The use of RDMA enables direct updates in member host memory without requiring member processor time. RDMA的使用支持成员主机内存中的直接更新,不需要成员处理器时间。
On an8 processor host, the best performance was observed with two two processor VMs when all processors are used for jobs. 在8处理器主机上,可以看到,当所有处理器用于处理任务时,有两个处理器性能最优。
This process is commonly called direct execution, because the instructions are executed directly by the host processor. 因为通过主机处理器直接执行指令,所以此过程通常被称为直接执行。
Terminal and host interface processor 终端与主机接口处理器
The host includes a memory and a center processor. 该主机包括一存储器与一中央处理器。
A debugging tool that runs on the host and pretends to be the target processor. 一种运行在主机上,装作目标机处理器的调试工具。
Bluetooth headsets, for example, combine the module and host portions of the stack on one processor because they need to be small and self-contained. 如,蓝牙头戴式耳机将协议的主机和模块部分结合在一个处理器,因为它们需要做得小巧和自我完备的。
Modules with microcontrollers in the system process their signals parallelly, and communicate with host processor by dual port memory. 以单片机为核心的各传感器接口模块并行处理各传感器信号,并通过双口存储器与上位处理器通信。
The Host Interface Design of Multi-DSP Processor 多DSP处理器HOST接口的硬件设计
A Distributed Control System Constructed With IBM PC as a Host Processor 以IBMPc为主处理机构成的分布式控制系统
A ping-pong memory was designed as the cache for the transfers between the host and the processor array, and four UART serial ports were extended. 设计了乒乓存储体用作主机和处理器阵列数据传输的缓冲区。另外还扩展出了4个UART串口。
In the hardware design, an communication host computer and its lower-position processor are made, which based on two-bus technology; 在硬件设计中,设计制作了基于二总线技术的通信主机及其下位机;
By thermal printing head control the characteristics of the ARM host processor hardware resources in-depth analysis, based on a simplified system design, improving system integration and reliability, to facilitate system software development principles, to determine the hardware selection of the printer driver and program determined. 通过对热敏打印头控制特点以及ARM主控芯片硬件资源的深入分析,基于简化系统设计、提高系统集成度和可靠性、方便系统软件开发的原则,确定了打印驱动的硬件选型和方案的确定。
Compared to the previous programs, this program greatly reduces the workload of the host processor FPGA, It is high real-time, modular and easy to expand. 减轻了主处理器FPGA的工作负担,并且具有实时性高、模块化、易于拓展等特点。
In the aspect of controlling of host processor, this system was simplified the interface of control logic, integrated auto-control circuit and auto-reset circuit what was run when system was in an anomalous state. 在主处理器控制方面,本系统内部集成自动控制和自动异常回复电路,简化了控制逻辑,大大减少了主处理器驱动的复杂程度。
The host processor is responsible for task scheduling, ultra-sound barrier, sensor and peripheral circuit, the slave processor is responsible for receiving data from the host processor and make motor realize the robot tasks. 主处理器主要负责任务调度、超声波避障、传感器及外围电路,从处理器负责接收主处理器传来的数据请求,控制电机做出适当的动作,实现机器人的作业任务。
Neuron Chip as a communications processor, Host processor deal with the application tasks. 主处理器处理应用程序任务,神经元芯片作为通信处理器。
When a large number of image data is needed for process, the host processor send instructions to the slave one, they work together and handle parallel. 当需要进行大量图像数据处理的时候,主处理器向从处理器发送相关指令,两个处理器协同工作,并行处理。